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# Created by write_sdc
# Mon Jul  8 14:51:32 2024
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current_design swerv_wrapper
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# Timing Constraints
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create_clock -name core_clock -period 2.0000 [get_ports {clk}]
set_propagated_clock [get_clocks {core_clock}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dbg_bus_clk_en}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_araddr[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arburst[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arburst[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arlen[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arlen[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arlen[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arlen[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arlen[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arlen[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arlen[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arlen[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arprot[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arprot[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arprot[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arsize[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arsize[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arsize[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awaddr[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awburst[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awburst[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awlen[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awlen[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awlen[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awlen[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awlen[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awlen[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awlen[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awlen[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awprot[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awprot[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awprot[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awsize[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awsize[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awsize[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_bready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[32]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[33]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[34]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[35]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[36]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[37]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[38]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[39]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[40]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[41]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[42]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[43]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[44]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[45]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[46]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[47]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[48]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[49]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[50]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[51]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[52]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[53]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[54]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[55]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[56]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[57]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[58]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[59]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[60]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[61]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[62]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[63]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wdata[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wlast}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wstrb[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wstrb[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wstrb[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wstrb[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wstrb[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wstrb[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wstrb[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wstrb[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_bus_clk_en}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {extintsrc_req[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {extintsrc_req[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {extintsrc_req[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {extintsrc_req[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {extintsrc_req[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {extintsrc_req[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {extintsrc_req[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {extintsrc_req[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {i_cpu_halt_req}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {i_cpu_run_req}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_bid[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_bid[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_bid[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_bresp[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_bresp[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_bvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[32]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[33]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[34]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[35]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[36]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[37]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[38]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[39]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[40]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[41]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[42]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[43]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[44]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[45]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[46]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[47]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[48]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[49]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[50]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[51]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[52]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[53]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[54]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[55]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[56]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[57]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[58]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[59]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[60]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[61]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[62]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[63]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rdata[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rid[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rid[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rid[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rlast}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rresp[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rresp[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_bus_clk_en}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_id[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_tck}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_tdi}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_tms}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_trst_n}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_bid[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_bid[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_bid[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_bid[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_bresp[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_bresp[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_bvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[32]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[33]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[34]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[35]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[36]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[37]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[38]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[39]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[40]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[41]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[42]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[43]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[44]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[45]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[46]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[47]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[48]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[49]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[50]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[51]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[52]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[53]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[54]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[55]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[56]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[57]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[58]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[59]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[60]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[61]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[62]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[63]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rdata[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rid[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rid[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rid[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rid[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rlast}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rresp[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rresp[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_bus_clk_en}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {mbist_mode}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {mpc_debug_halt_req}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {mpc_debug_run_req}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {mpc_reset_run_req}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_int}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {nmi_vec[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_l}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {rst_vec[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_bid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_bresp[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_bresp[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_bvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[10]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[11]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[12]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[13]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[14]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[15]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[16]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[17]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[18]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[19]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[20]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[21]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[22]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[23]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[24]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[25]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[26]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[27]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[28]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[29]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[2]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[30]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[31]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[32]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[33]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[34]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[35]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[36]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[37]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[38]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[39]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[3]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[40]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[41]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[42]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[43]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[44]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[45]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[46]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[47]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[48]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[49]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[4]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[50]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[51]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[52]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[53]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[54]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[55]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[56]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[57]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[58]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[59]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[5]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[60]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[61]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[62]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[63]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[6]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[7]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[8]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rdata[9]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rlast}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rresp[0]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rresp[1]}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rvalid}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wready}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {scan_mode}]
set_input_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {timer_int}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {debug_brkpt_status}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dec_tlu_perfcnt0[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dec_tlu_perfcnt0[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dec_tlu_perfcnt1[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dec_tlu_perfcnt1[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dec_tlu_perfcnt2[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dec_tlu_perfcnt2[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dec_tlu_perfcnt3[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dec_tlu_perfcnt3[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_arready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_awready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_bid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_bresp[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_bresp[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_bvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[32]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[33]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[34]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[35]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[36]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[37]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[38]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[39]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[40]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[41]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[42]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[43]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[44]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[45]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[46]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[47]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[48]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[49]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[50]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[51]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[52]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[53]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[54]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[55]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[56]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[57]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[58]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[59]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[60]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[61]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[62]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[63]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rdata[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rlast}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rresp[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rresp[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_rvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {dma_axi_wready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_araddr[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arburst[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arburst[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arcache[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arcache[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arcache[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arcache[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arid[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arid[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arid[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlen[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlen[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlen[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlen[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlen[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlen[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlen[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlen[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arlock}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arprot[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arprot[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arprot[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arqos[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arqos[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arqos[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arqos[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arregion[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arregion[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arregion[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arregion[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arsize[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arsize[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arsize[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_arvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awaddr[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awburst[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awburst[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awcache[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awcache[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awcache[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awcache[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awid[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awid[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awid[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlen[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlen[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlen[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlen[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlen[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlen[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlen[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlen[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awlock}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awprot[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awprot[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awprot[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awqos[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awqos[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awqos[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awqos[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awregion[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awregion[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awregion[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awregion[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awsize[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awsize[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awsize[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_awvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_bready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_rready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[32]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[33]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[34]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[35]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[36]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[37]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[38]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[39]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[40]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[41]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[42]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[43]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[44]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[45]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[46]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[47]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[48]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[49]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[50]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[51]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[52]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[53]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[54]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[55]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[56]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[57]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[58]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[59]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[60]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[61]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[62]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[63]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wdata[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wlast}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wstrb[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wstrb[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wstrb[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wstrb[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wstrb[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wstrb[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wstrb[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wstrb[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {ifu_axi_wvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {jtag_tdo}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_araddr[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arburst[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arburst[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arcache[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arcache[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arcache[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arcache[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arid[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arid[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arid[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arid[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlen[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlen[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlen[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlen[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlen[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlen[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlen[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlen[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arlock}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arprot[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arprot[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arprot[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arqos[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arqos[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arqos[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arqos[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arregion[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arregion[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arregion[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arregion[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arsize[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arsize[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arsize[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_arvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awaddr[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awburst[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awburst[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awcache[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awcache[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awcache[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awcache[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awid[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awid[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awid[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awid[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlen[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlen[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlen[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlen[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlen[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlen[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlen[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlen[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awlock}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awprot[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awprot[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awprot[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awqos[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awqos[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awqos[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awqos[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awregion[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awregion[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awregion[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awregion[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awsize[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awsize[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awsize[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_awvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_bready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_rready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[32]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[33]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[34]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[35]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[36]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[37]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[38]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[39]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[40]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[41]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[42]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[43]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[44]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[45]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[46]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[47]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[48]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[49]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[50]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[51]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[52]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[53]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[54]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[55]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[56]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[57]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[58]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[59]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[60]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[61]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[62]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[63]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wdata[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wlast}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wstrb[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wstrb[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wstrb[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wstrb[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wstrb[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wstrb[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wstrb[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wstrb[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {lsu_axi_wvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {mpc_debug_halt_ack}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {mpc_debug_run_ack}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {o_cpu_halt_ack}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {o_cpu_halt_status}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {o_cpu_run_ack}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {o_debug_mode_status}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_araddr[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arburst[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arburst[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arcache[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arcache[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arcache[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arcache[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlen[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlen[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlen[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlen[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlen[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlen[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlen[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlen[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arlock}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arprot[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arprot[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arprot[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arqos[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arqos[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arqos[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arqos[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arregion[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arregion[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arregion[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arregion[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arsize[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arsize[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arsize[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_arvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awaddr[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awburst[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awburst[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awcache[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awcache[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awcache[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awcache[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlen[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlen[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlen[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlen[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlen[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlen[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlen[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlen[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awlock}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awprot[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awprot[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awprot[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awqos[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awqos[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awqos[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awqos[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awregion[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awregion[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awregion[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awregion[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awsize[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awsize[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awsize[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_awvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_bready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_rready}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[32]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[33]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[34]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[35]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[36]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[37]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[38]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[39]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[40]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[41]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[42]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[43]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[44]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[45]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[46]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[47]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[48]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[49]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[50]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[51]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[52]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[53]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[54]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[55]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[56]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[57]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[58]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[59]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[60]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[61]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[62]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[63]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wdata[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wlast}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wstrb[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wstrb[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wstrb[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wstrb[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wstrb[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wstrb[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wstrb[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wstrb[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {sb_axi_wvalid}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[32]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[33]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[34]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[35]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[36]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[37]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[38]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[39]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[40]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[41]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[42]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[43]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[44]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[45]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[46]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[47]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[48]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[49]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[50]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[51]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[52]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[53]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[54]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[55]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[56]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[57]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[58]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[59]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[60]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[61]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[62]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[63]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_address_ip[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_ecause_ip[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_ecause_ip[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_ecause_ip[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_ecause_ip[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_ecause_ip[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_exception_ip[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_exception_ip[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_exception_ip[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[32]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[33]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[34]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[35]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[36]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[37]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[38]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[39]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[40]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[41]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[42]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[43]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[44]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[45]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[46]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[47]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[48]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[49]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[50]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[51]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[52]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[53]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[54]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[55]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[56]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[57]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[58]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[59]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[60]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[61]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[62]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[63]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_insn_ip[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_interrupt_ip[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_interrupt_ip[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_interrupt_ip[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[10]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[11]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[12]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[13]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[14]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[15]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[16]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[17]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[18]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[19]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[20]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[21]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[22]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[23]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[24]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[25]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[26]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[27]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[28]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[29]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[2]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[30]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[31]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[3]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[4]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[5]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[6]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[7]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[8]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_tval_ip[9]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_valid_ip[0]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_valid_ip[1]}]
set_output_delay 0.4000 -clock [get_clocks {core_clock}] -add_delay [get_ports {trace_rv_i_valid_ip[2]}]
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# Environment
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# Design Rules
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